Integrated circuits (ICs) often contain millions of transistors and millions of interconnections. To verify that these transistors and interconnections operate as intended, they must be tested. Many testing techniques may be used to verify the operation of an IC.
For example, broadside testing includes electrically stimulating the inputs of an IC and measuring the outputs of the IC to determined if the output matches the predicted output. In the case where the predicted output matches the measured output, the IC may be functioning correctly. However, this test alone does not guarantee that the IC will function 100 percent correctly. More tests are needed to verify that the IC is operating as designed.
In the case where broadside testing is used and the measured output does not match the predicted output, the IC may not be operating correctly. This type of testing indicates that there may be problems with the IC. However, this type of testing usually does not indicated what in particular caused the IC to operate incorrectly. To better diagnose what may be causing the IC to fail, internal scan testing may be used.
Internal scan testing provides a means to test interconnections and transistors without using physical test probes. Internal scan testing usually adds one or more so called ‘test cells’ connected to each pin of an IC that can selectively override the functionality of that pin. These cells can be programmed via a JTAG (Joint Test Action Group) test chain to drive a signal onto a pin and across an individual interconnection. The cell at the destination of the interconnection can then be programmed to read the value at the pin, verifying that the IC trace properly connects the two pins. If the trace is shorted to another signal or if the trace has been cut, the correct signal value may not be presented at the destination pin, and the IC will be observed to have a fault.
Because these cells can be used to force data into an IC, they may be used to set up test conditions. The relevant electronic states (ones and zeros) created as a result of the test conditions, may then be fed back into a test system to verify the functionality of a part of an IC. By adopting this technique, it is possible for a test system to gain test access to many parts of an IC. However, the additional circuitry added to an IC in order to enable internal scan testability may have functional problems as well. The additional circuitry added to an IC in order to enable internal scan testability must be tested as well in order to increase the probability that the IC functions as designed.